1. Field of the Invention
The invention relates to the field of signal communications between electronic circuits. More specifically, the invention is directed to a versatile input/output (I/O) buffer for interfacing one electronic circuit with other electronic circuits which may be operating with different power supply levels and/or signaling voltage ranges.
2. Description of Prior Art
Any given electronic circuit or component in the modern age is often required to communicate with a wide variety of other electronic circuits or components which have different power supply levels and/or signaling voltage ranges.
Several prior art attempts have been made to accommodate the different signal voltage ranges encountered when interfacing different electronic circuits. One such attempt provides separate I/O buffers for each signaling voltage range that is likely to be used by external circuits. As shown in FIG. 4a, for example, it is known to provide separate I/O buffers 40, 42 for use with the same input/output terminal (shown as "pad 44") of a field programmable gate array (FPGA) 18 integrated circuit (IC) which connects with external circuits or components 21. It should be understood that the FPGA is merely illustrative of just one type of circuit which may be required to interface with other electronic circuits or components.
As is well known in the art, some I/O buffer circuits utilize separate buffers for input and output stages, whereas others integrate the two functions into a single buffer circuit. The FPGA 18 illustrated in FIG. 4a is configured for use with external circuits or components 21 utilizing one of two different signaling voltage ranges having upper voltages rated at 3.3 volts (V) and 5 V. To the extent that any electronic circuit or component used with the FPGA 18 utilizes a 5 V signaling voltage range, the I/O 5 V buffer 40 is used to couple that electronic component to the FPGA's pad 44. To the extent that an electronic component utilizes a 3.3 V signaling voltage range, the I/O 3.3 V buffer 42 would be used to couple that electronic component to the pad 44.
Another prior art I/O buffer circuit, shown in FIG. 4b, is capable of supporting and tolerating different signaling voltage ranges of external components. To the extent that a 5 V signaling voltage range-based electronic component is used with the FPGA, the configurable I/O buffer 46 is configured to accept or output signals compatible with the 5 V environment of the electronic component. To the extent that the electronic component uses a 3.3 V signaling voltage range scheme, the I/O buffer 46 is configured to accept or output signals compatible with the 3.3 V environment of the electronic component. In order to discriminate between the different power supply levels and/or signaling voltage ranges in the particular electronic component used with the FPGA, a memory cell 48, e.g., a RAM cell (as shown in FIG. 4b) or ROM cell, is provided to store and output a voltage designation bit identifying the signaling voltage range used in the electronic component. Based on this identification bit, the I/O buffer 46 is configured to accept or output either 5 V or 3.3 V-based signals accordingly.
In both systems described above, the operating voltage range of the electronic component attached to the input of the I/O buffer must be known in advance. For example, in the dual I/O buffer arrangement, shown in FIG. 4a, the user must know the pertinent operating signaling voltage range to determine which one of the two I/O buffers 40, 42 should be connected to pad 44. Similarly, in the FIG. 4b single buffer arrangement, the user must know the operating signaling voltage range of the electronic component in advance in order to store the correct designation bit in memory cell 48. These proposed solutions thus have no capability of adapting the I/O buffer to an electronic component which has a signaling voltage range which is unknown prior to attachment to the FPGA system.